This invention relates to a stacked semiconductor package and, in particular, to a stacked DRAM package allowing high-speed data transfer.
Referring to FIG. 1, a conventional stacked semiconductor package comprises stackable semiconductor packages. Each of the stackable semiconductor package comprises a substrate 102 provided with a cavity 101 formed on a center portion of a top surface thereof, a wiring pattern 103 extending from the top surface to a bottom surface of the substrate 102, a semiconductor chip 104 disposed in the cavity 101 of the substrate 102, a plurality of bonding wires 105 connecting the semiconductor chip 104 to the wiring pattern 103, and a plurality of terminal pads 106 formed on the top surface of the substrate 102 and connected to the wiring pattern 103, and a plurality of solder balls 107 formed on the bottom surface of the substrate 102 to be connected and fixed to the wiring pattern 103.
The terminal pads 106 are arranged in a pattern identical to that of the solder balls 107. In other words, the terminal pads 106 and the solder balls 107 are arranged so that, if a plurality of such stackable semiconductor packages are prepared and stacked on one another, the solder balls 107 of an upper package are faced in one-to-one correspondence to the terminal pads 106 of a lower package adjacent thereto. Therefore, by stacking a plurality of stackable semiconductor packages and carrying out a reflowing process, it is possible to obtain the stacked package in which a plurality of semiconductor chips are stacked and connected to one another (for example, see Japanese Patent Application Publication (JP-A) No. H11-220088).
Referring to FIG. 2, another conventional stacked semiconductor package comprises semiconductor chips 111 and flexible substrates 112 wrapping the semiconductor chips 111 separately.
Referring to FIG. 3, each of the semiconductor chips 111 of the stacked semiconductor package illustrated in FIG. 2 has a bottom surface provided with a plurality of contacts 121. On the other hand, each of the flexible substrate 112 has a top surface provided with a first conductive pad array 122 arranged in a pattern (reversed pattern) corresponding to that of the contacts 121. The flexible substrate 112 has a bottom surface provided with a second conductive pad array overlapping and aligned with the first conductive pad array 122 in a vertical direction (i.e., arranged in a pattern identical to that of the contacts 121), and third and fourth conductive pad arrays formed on opposite sides of the second conductive pad array. Each of the third and the fourth conductive pad arrays is arranged in a reversed pattern with respect to a corresponding half of the second conductive pad array and is connected to the corresponding half of the second conductive pad array through a wiring pattern.
When the semiconductor chip 111 is mounted on the top surface of the flexible substrate 112, the contacts 121 of the semiconductor chip 111 are connected to first conductive pads of the first conductive pad array 122 on the top surface of the flexible substrate 112 and, through the flexible substrate 112, are also connected to second conductive pads of the second conductive pad array located on the bottom surface of the flexible substrate 112. As a consequence, each of the contacts 121 of the semiconductor chip 111 is connected to a corresponding one of the pads contained in the third or the fourth conductive pad array. When the flexible substrate 112 is folded so as to wrap the semiconductor chip 111, the third and the fourth conductive pad arrays are positioned above a top surface of the semiconductor chip. That is, the third and the fourth conductive pad arrays face up. A fifth conductive pad array defined by the third and the fourth conductive pad arrays is arranged in a pattern identical to that of the first conductive pad array. Thus, the semiconductor chip 111 and the corresponding flexible substrate 112 form a stackable semiconductor package.
By stacking a plurality of stackable semiconductor packages having the above-mentioned structure and heating the packages stacked on one another, the second conductive pad array of an upper package and the fifth conductive pad array of a lower package adjacent thereto are connected by soldering to each other. As a result, the stacked package comprising the semiconductor packages stacked on one another and connected to one another is obtained as illustrated in FIG. 2 (for example, see U.S. Pat. No. 6,473,308).
Each of the conventional stacked semiconductor packages described above comprises stackable semiconductor packages each of which comprises the single substrate and the single semiconductor chip mounted thereto. That is, by stacking the stackable semiconductor packages, the stacked semiconductor package is obtained. In the stacked package, pins (solder balls or conductive pads) of the lowermost stackable semiconductor package are used as external connection terminals (stacked package pins) while pins of each of the remaining stackable semiconductor packages are used for connection to a lower adjacent one of the stackable semiconductor packages. Therefore, a wiring distance between the pins of each of the stackable semiconductor packages forming the stacked package and the external connection terminals depends upon a stacked position of each stackable semiconductor package in a vertical direction. Specifically, an upper package has a longer wiring distance and a lower package has a shorter wiring distance. Thus, the conventional stacked semiconductor packages are disadvantageous in that the distance to the external connection terminals is different depending upon the stacked position of each stackable semiconductor package.